As integrated circuits increase in size and complexity, techniques which reduce the space needed for an individual circuit without adding undue processing complexity continue to be important. In devising appropriate processing sequences, attention must be given, not only to the fabrication of the individual devices in the circuit, but also to how the devices will be electrically contacted and connected to each other. The considerations associated with electrical contacts and interconnections are important for all integrated circuits, including static random access memories which are commonly referred to by the acronym SRAM.
Such memories typically use a memory cell with either six field-effect transistors or with four such transistors and two load resistors. Two of the transistors are connected to form a flip-flop; i.e., the gate and source/drain region of the first transistor are connected to the source/drain region and gate, respectively, of the second transistor. This connection is typically fabricated from polysilicon. Although polysilicon is electrically conductive, better attributes, such as lower contact resistance, could be expected if a silicide could be used. Each cell stores one bit of information in a single word and is accessed through word and bit lines.
In many prior art circuits, the gate contact to an individual transistor is made over the field oxide to a gate runner which extends from the active device regions onto the field oxide. This type of contact is also used in types of integrated circuits other than SRAMs. Although this contact results in a less economical use of space than if the gate were contacted directly over the active device regions, it is widely used because of difficulties encountered in electrically contacting the gate over the active device region without inadvertently and disastrously contacting the active device regions located on opposite sides of the gate structure. These difficulties become greater as device dimensions decrease, i.e., as feature dimensions become smaller and the tolerances for registration errors decrease. Of course, even if the gate structure is contacted over the field oxide, a small window exposing the gate structure is desirable because it minimizes any problems that might arise from window misalignment with respect to the gate and source/drain regions.